What a strapping pin is
When the chip leaves reset it latches the logic level of a few GPIOs and uses them to choose the boot mode, the flash supply voltage and whether the ROM prints boot messages. A moment later those pins are ordinary GPIOs again. That is why the mistake is so easy to make: a pull-up resistor, an LED, an I2C pull-up or a peripheral input that happens to sit on a strapping pin is a perfectly valid connection electrically, and KiCad's ERC has no reason to complain. The problem only exists for the few microseconds when the level is sampled.
Each strapping pin has a weak internal pull-up or pull-down that sets its default. Anything you connect can overpower that default, so the rule of thumb is: leave strapping pins alone, or make sure whatever you connect cannot force the wrong level during reset.
The EN (CHIP_PU) reset circuit
EN, called CHIP_PU on newer datasheets, enables the chip. It must not float, and it should rise only after the 3.3 V supply is stable. Espressif's hardware design guidelines recommend an RC delay of R = 10 kΩ from EN to 3V3 and C = 1 µF from EN to GND, tuned to your supply's ramp if needed. The same recommendation appears in the checklists for the ESP32, S2, S3, C3 and C6.
- Put the reset button from EN to GND, in parallel with the capacitor.
- If you use a USB-UART bridge with the classic two-transistor auto-reset circuit, its EN transistor goes on the same net.
- Tying EN straight to 3V3 usually works on a bench supply and fails with a slow-rising USB or battery rail: the chip starts before the voltage is valid and hangs or boot-loops.
Strapping pins by chip family
The table summarises the pins that matter when designing a board. "Download" means the ROM serial/USB bootloader used for flashing.
| Family | Pins | What to watch |
|---|---|---|
| ESP32 | GPIO0, GPIO2, GPIO12 (MTDI), GPIO15 (MTDO), GPIO5 | Download needs GPIO0 = 0 and GPIO2 = 0 or floating. GPIO12 high selects a 1.8 V flash supply. GPIO15 low silences the boot log. |
| ESP32-S2 | GPIO0, GPIO45, GPIO46 | Download needs GPIO0 = 0 and GPIO46 = 0. GPIO45 selects the VDD_SPI (flash) voltage. |
| ESP32-S3 | GPIO0, GPIO3, GPIO45, GPIO46 | Download needs GPIO0 = 0 and GPIO46 = 0. GPIO45 = 1 selects 1.8 V VDD_SPI. GPIO3 only matters if JTAG eFuses are burned. |
| ESP32-C3 | GPIO2, GPIO8, GPIO9 | GPIO9 is the boot button pin (0 = download). Download also needs GPIO8 = 1; GPIO2 should be pulled up. |
| ESP32-C6 | GPIO8, GPIO9, GPIO15, MTMS, MTDI | GPIO9 = 0 with GPIO8 = 1 enters download; GPIO8 = 0 and GPIO9 = 0 together is invalid. |
ESP32: the GPIO12 trap
On the original ESP32, MTDI (GPIO12) selects the voltage of the VDD_SDIO rail that powers the flash. It has an internal pull-down, so by default the flash gets 3.3 V. Pull GPIO12 high at reset - with a pull-up, an SD-card data line or a peripheral that idles high - and the chip switches the flash to 1.8 V. Almost every ESP32-WROOM module uses 3.3 V flash, so the board browns out the flash and fails to boot or to flash. If you truly need GPIO12 high at boot, Espressif's tools can burn an eFuse that fixes the flash voltage at 3.3 V, but that is a one-way change to every chip you build.
GPIO2 has the opposite requirement: it must be low or floating for the bootloader. An SD card in 1-bit or 4-bit mode puts a pull-up on DAT0, which is GPIO2, and blocks flashing unless GPIO2 is pulled low together with GPIO0.
ESP32-S2 and ESP32-S3: GPIO45 and GPIO46
GPIO45 plays the same role as GPIO12 on the ESP32: high at reset selects 1.8 V for VDD_SPI. Unless your module uses 1.8 V flash and PSRAM, keep GPIO45 low (its default). GPIO46 has an internal pull-down and must be low to enter the download mode; GPIO0 low with GPIO46 high is not a valid boot combination. Both are fine to use for inputs that are idle-low or for outputs, as long as nothing drives them high during reset.
ESP32-C3 and ESP32-C6: GPIO8 and GPIO9
On these RISC-V parts, GPIO9 is the boot pin that a BOOT button pulls to ground. Download mode also needs GPIO8 high, and on the C3 GPIO8 has no default pull, so a load that drags it low (an LED to ground, a pull-down, a peripheral input) can make the bootloader impossible to reach. The ESP32-C3 datasheet also recommends pulling GPIO2 up to avoid glitches.
Other pins that are not strapping pins but still bite
- Flash and PSRAM pins. On ESP32 modules, GPIO6 to GPIO11 run the internal SPI flash (and GPIO16/17 the PSRAM on WROVER modules). On ESP32-S3 parts with octal PSRAM, GPIO33 to GPIO37 are taken. Connecting anything there crashes the chip.
- Input-only pins. ESP32 GPIO34 to GPIO39 cannot drive outputs and have no internal pull-ups; a button on them needs an external resistor.
- A way to program. Bring U0TXD/U0RXD, EN and the boot pin to a header, a USB-UART bridge or test points - or on S2/S3/C3/C6 route the native USB pins to the connector.
A short checklist
- EN: 10 kΩ to 3V3, 1 µF to GND, reset button to GND.
- Boot pin (GPIO0, or GPIO9 on C3/C6): pull-up, BOOT button to GND or an auto-program circuit, no large capacitor on the pin.
- List every net on a strapping pin and ask what level it has during reset.
- Keep LEDs, pull-ups and SD cards off GPIO12, GPIO45 and GPIO46 unless you have checked the boot level.
- Leave the flash/PSRAM pins unconnected.
The checker applies these rules automatically: EN RC, boot pin, strapping pins, flash pins, input-only pins and programming path.
Primary sources
- Espressif ESP32 Hardware Design Guidelines - Schematic Checklist (also available for the S3, S2, C3 and C6)
- esptool documentation - Boot Mode Selection
- ESP32 Series Datasheet (strapping pin table and default pulls)
This guide is a design aid, not engineering advice. Always confirm pin behaviour in the datasheet for your exact chip and module revision.