Free KiCad schematic checker
Catch the ESP32, STM32 and USB-C mistakes before you pay for boards.
Drop a KiCad netlist or schematic. 31 deterministic checks run in your browser and explain every finding: why it matters, how to fix it, and the datasheet or application note it comes from.
- Your file never leaves your browser
- Free, no signup, no install
- KiCad 6 to 10
Drop your .net or .kicad_sch files here
A netlist is the exact path. For a hierarchical schematic, select every .kicad_sch file of the project.
No file handy? Try a sample board:
Need the file? File > Export > Netlist > KiCad > Export
What it checks
Rules target the mistakes that actually stop boards from working - the ones people ask about in "review my schematic" threads - not cosmetic style issues. See all 31 rules.
USB and USB-C (5)
- Separate 5.1 kΩ on CC1 and CC2 (no shared resistor)
- D+/D- on both rows, and not swapped at the chip
- ESD array and series-resistor sanity
ESP32 family (6)
- EN pull-up + RC delay (10 kΩ + 1 µF)
- Strapping pins: GPIO12, GPIO45/46, C3/C6 GPIO8
- Flash/PSRAM pins, GPIO34-39 input-only, programming path
STM32 (7)
- BOOT0 pull-down, NRST 100 nF, VBAT
- VDDA decoupling and VCAP capacitors (F4/F7/H7)
- SWD access, STM32F1 1.5 kΩ USB pull-up
Power (5)
- Decoupling capacitors per IC power pin
- Regulator input/output and bulk capacitors
- Look-alike rails ("3V3" vs "+3.3V"), floating grounds
Clocks, buses and MCU pins (4)
- Crystal load capacitors, with the CL maths
- I2C pull-ups sized per the NXP spec
- UART TX-to-TX, 5 V on 3.3 V pins
Parts and nets (4)
- LEDs without current limiting
- MOSFET gates that float during reset
- Labels that reach one pin (typos), floating IC pins
How it works
Export a netlist
In the KiCad Schematic Editor: File > Export > Netlist, keep the KiCad format, Export. Or skip this and drop the .kicad_sch files.
Drop it on the page
Parsing and all 31 rules run locally in JavaScript. A typical board takes well under a second, and the results show the measured time.
Fix, then fab
Each finding lists the parts and nets involved, why it matters, how to fix it and a primary reference. Copy the report as Markdown for a Reddit or GitHub post.
Why not just run ERC?
You should run KiCad's electrical rules check too. It answers a different question.
| Question | KiCad ERC | Before You Fab |
|---|---|---|
| Are pins connected, and are pin types compatible? | Yes | Partly (floating IC power pins, one-pin labels) |
| Is GPIO12 on my ESP32 pulled high at boot? | No - it is a valid connection | Yes, with the flash-voltage explanation |
| Does my USB-C port power up from a C-to-C charger? | No | Yes: checks Rd on CC1 and CC2 |
| Will my STM32 boot my code and not the ROM bootloader? | No | Yes: BOOT0, NRST, VCAP, VDDA |
| Does it need my files on a server? | No (desktop) | No (runs in your browser) |
Checked against KiCad itself
The .kicad_sch reader computes connectivity from symbol pins, wires, labels, power symbols, buses and hierarchical sheets. It was compared with kicad-cli sch export netlist (KiCad 7.0.11) on 19 projects - six open-source ESP32, ESP32-S3, ESP32-C3, RP2040 and STM32F405 boards from GitHub, KiCad's demo projects and edge-case tests: 2,428 of 2,428 nets matched, including net names and no-connect flags.
Every rule has unit tests with passing and failing examples, and the rules are regression-tested on those real open-source designs to keep false alarms rare.
Private by design
There is no upload endpoint. The checker is static files served from a CDN; your design is parsed in memory in this tab and discarded when you close it.
Analytics are cookieless and only record events such as "a check ran with 22 parts and 1 error" - never names, values or files. Privacy policy.
Want a human to review it before you order?
Rules catch the classic mistakes. A pre-fab review also catches the ones specific to your design. Built by Mahir Patel, an electrical-engineering student at the University of Illinois Urbana-Champaign. Limited to a few reviews per week.
Schematic Check
$149
Schematic only, up to about 60 parts. Report in 3 business days.
Request Schematic CheckFull Review
$299
Schematic + PCB layout from your KiCad files. Report in 4 business days.
Request Full ReviewPre-Fab Sign-off
$549
Full Review + a check of the exact fab package you will order. Report in 6 business days.
Request Pre-Fab Sign-offQuestions
Is my schematic uploaded anywhere?
No. The file is read with your browser's File API and checked by JavaScript running in this tab. The page never sends file contents, file names, part values or net names anywhere. Anonymous usage counts (for example "a check ran: 22 parts, 1 error") are recorded without cookies, as described in the privacy policy. Open your browser's network panel while a check runs: no request carries your file.
Which KiCad versions work?
Netlists (.net) exported by KiCad 6, 7, 8, 9 and 10 in the default "KiCad" format - KiCad 5 netlists also parse. You can also drop .kicad_sch files directly (select every sheet of a hierarchical project). The schematic reader matched KiCad 7's own netlist export on all 2,428 nets of 19 test projects; a netlist is still the exact path, especially for files saved by KiCad 8 or newer.
Does this replace KiCad's ERC or a design review?
No. KiCad's ERC checks connectivity and pin types; these rules check design intent for specific, well-documented failure modes (strapping pins, USB-C CC resistors, BOOT0, decoupling and so on). Neither sees your layout, your firmware or your use case. Treat findings as a checklist, not a sign-off.
What if a finding is wrong for my board?
Rules are heuristics built from datasheets and application notes, and each one explains the assumption it makes. When a rule is unsure it reports "info" instead of an error. If you hit a false positive, use the "Report a false positive" link under the finding - it only sends what you type.
Is it really free? Can I use it for commercial projects?
Yes and yes. The checker is free with no account and no limits. It is funded by the optional human pre-fab reviews on the pricing page.
What does the paid human review add?
A person reads your whole schematic (and, in the higher tiers, your PCB layout and fab files) against the datasheets, looks for mistakes no rule can know about, and sends a written report with fixes. Tiers start at $149 with a 3 business day turnaround.