Before You Fab

Fab-order check for KiCad and JLCPCB

Check your KiCad board before you pay a fab to build it wrong.

Drop your schematic, board file, BOM and placement CSV. 38 checks run in this tab on the exact files you are about to upload, and nothing leaves your computer. When you want a person to sign off the order, it is $49.

  • Runs in your browser, no upload
  • Free, no account
  • Reads KiCad 6 to 10 (KiCad 5: board and netlist)
  • Every finding shows its evidence
Drop your KiCad project here A folder, a .zip, or files: .kicad_sch .kicad_pcb .kicad_pro and the BOM and placement .csv files

Runs in this tab. No upload, no account, no analytics or other third-party script on this page. How to verify that. On a phone, pick a .zip of the project.

What it catches

The mistakes that cost a whole order

A respin is the entire order again plus weeks of waiting. These are the errors that survive ERC and DRC and show up when the boards arrive. The examples are from the sample report, a real open-source board.

Files that disagree

Schematic, board, BOM and placement file are four exports that drift apart. The check lines them up: parts missing from the board, nets that differ, BOM lines with no placement, two footprints sharing one reference, malformed LCSC numbers.

Rules: pcb-sync, cpl-vs-pcb, bom-cpl-match, bom-vs-design, duplicate-refs, bom-lcsc

Features the fab will flag

JLCPCB’s published limits, read from your board whatever your own design rules say: annular ring, drill size, track width, silkscreen, outline. It does not measure the gap between tracks; run KiCad’s DRC with JLCPCB’s minimum clearance for that. It also tells you whether the board qualifies for Economic PCBA or needs Standard.

Sample: 15 plated holes have an annular ring under 0.18 mm on U1 (thinnest 0.075 mm).

Parts missing their basics

The things a reviewer looks at around every IC: bypass capacitors, regulator input and output capacitors, crystal load capacitors, I2C pull-ups, USB-C CC resistors, EN and BOOT pins, ESD on USB, MOSFET gates.

Sample: an LDO with no capacitor on its output, and a charger with none on either side.

Proof

A real report on a real board

This is the output for joric/nrfmicro, a public-domain open-source board. Seven serious findings. I opened the files and confirmed each one by hand, and the report says so next to each finding.

Labeled sample, not a client board. Not a statement about the quality of the original project.

Fix first4 things to fix before you order4 blockers 3 warnings 4 notes
U2 (AP2112K-3.3) has no capacitor on its output net nRF_VDDBlocker, reg-capsChecked by hand: confirmed
15 plated holes have an annular ring under 0.18 mm on U1 (thinnest 0.075 mm)Blocker, jlc-limitsChecked by hand: confirmed
Input "PROG" on U1 pin 15 (P0.05/AIN3) has a label but nothing drives itWarning, orphan-labelChecked by hand: confirmed

Accuracy, stated plainly

What it got wrong, and by how much

I measured it on open-source boards it had never seen, and checked every serious finding by hand. The numbers below are the latest untouched run, not a tuned one.

29serious findings (blockers and warnings) on boards it had never seen
12real problems the owner should fix
9true but harmless or intentional
8wrong, listed with the cause on the accuracy page

72% correct, 41% worth acting on. That is why every finding has an evidence line and why the paid tier has a person who confirms or dismisses each one. Seeded-bug test: when I removed a part from 29 real boards it had not been tuned on, it noticed 235 of 246 times. Method, misses and all 38 rules.

Who is behind this

Mahir Patel

UIUC electrical engineering student. I design boards in KiCad and order them assembled from JLCPCB.

  • Paid client work in September 2026: a USB-C protection front end, and a battery power-switch board delivered as a JLCPCB package for 50 assembled boards.
  • Paid client work in October 2026: a 4-layer, 88-part two-speed PWM controller, with JLCPCB assembly files for both sides.

It is one person’s tool, not a company’s: you deal with me, and I answer by email.

Questions

Before you try it

Does my design get uploaded?

No. The checker is JavaScript that runs in this tab. This page loads no analytics and no other third-party script, and its security policy lets it talk only to this site, so it cannot send your files to anyone else. You can check: open your browser’s developer tools, go to the Network tab, drop a board, and watch. Files leave your computer only if you choose to send them to me for a paid review.

KiCad has ERC and DRC, and JLCPCB runs a DFM check. What does this add?

Use all three. They answer different questions.

  • KiCad ERC/DRC checks electrical and layout rules against your rule set, which most people leave at the defaults. This checks the published JLCPCB limits (annular ring, drill, silkscreen, outline) whatever your settings are.
  • JLCPCB’s DFM is authoritative on JLCPCB’s own process and is free. It only sees Gerbers, BOM and placement after you are in their order flow, and it never sees your schematic. It cannot tell you that a regulator has no output capacitor or that a net carries two different names.
  • This check lines the four files up against each other (schematic, board, BOM, placement), then checks the parts around each IC the way a reviewer would. It is made to run before you open the order page.
How accurate is it?

Honest answer from the latest test on boards it had never seen: of 29 serious findings, 12 were real problems, 9 were true but harmless, and 8 were wrong (72% correct, 41% worth acting on). I then fixed the wrong ones. That fix is not counted as accuracy, because I looked at those boards first. Every finding names its rule and shows the nets or parts involved so you can check it in a minute. Full numbers, including the misses.

What does the $49 check cover that the free one cannot?

The free report ends with a list called “Still needs a person”. That list is the product. On your board it covers: BOM parts against JLCPCB’s live parts library (stock, lifecycle, Basic or Extended fee), pin-1 and polarity rotation for every polarised part, footprints that did not ship with KiCad against the datasheet land pattern, and every free finding confirmed or dismissed by hand. You get a one-page order-it-or-fix-these-first note.

Which files do I need?

Best: the schematic (all sheets), the .kicad_pcb, and the BOM and placement CSVs in JLCPCB’s format. A schematic alone works, and so does a netlist (.net). Checks that need a file you did not give are shown as not run, never as passed. A .zip of the project folder works too. On KiCad 8 and newer, include the .kicad_pro project file as well: bus aliases are stored there, and without it a bus drawn from an alias is not expanded.

Can I use it for Altium, Eagle or EasyEDA, or an older KiCad?

Not for Altium, Eagle or EasyEDA. KiCad only: schematics (.kicad_sch) and boards from KiCad 6 to 10 are read directly. KiCad 5 keeps its schematic in the old .sch format, which this does not read. For a KiCad 5 project, export a netlist (.net) from the schematic and give it to the checker together with the .kicad_pcb and the BOM and placement files; the netlist stands in for the schematic.

Who reads my board?

I do. Mahir Patel: UIUC electrical engineering student. I design boards in KiCad and order them assembled from JLCPCB. I use the same checker you just ran, then do the parts it cannot. More about me.

What if you find nothing?

Then I say so, and what I checked. A review lowers risk; it does not guarantee a working board. If it tells you nothing you did not already know, you get your money back.

Order it once, correctly.

Run the free check now. If it finds something, fix it. If you want someone to read the order before you pay for it, send me the board.