Sample report

A real report on a real open-source board

This is what the free check produced from the files of joric/nrfmicro. After the software ran, I opened the project files and confirmed each blocker and warning by hand. Those notes are in green.

Run this check yourself in the browser Download the files

Sample report, open-source board

nrfmicro (sample)

24 parts, 50 nets, 25 footprints, 20 BOM lines, 25 placements

Fix first 4 things to fix before you order 4 blockers 3 warnings 4 notes

What was checked

Schematic / netlist
Board file
BOM
Placement CSV

38 of 38 checks ran on these files. This sample was produced by the same checker you can run on the home page, on the files linked on this page.

Fix before you order 4

Blocker

15 plated holes have an annular ring under 0.18 mm on U1 (thinnest 0.075 mm)

JLCPCB's absolute minimum PTH annular ring is 0.18 mm for 2-layer 1 oz; 0.25 mm is recommended.

Why it matters: Drill tolerance can leave the hole breaking out of the pad, which gives an unreliable joint or an open.
Fix: Enlarge the pad or choose a footprint with a bigger pad for this lead diameter.

Checked by hand: Confirmed. The E73 module footprint has 15 through-hole pads, each a 0.65 x 1.0 mm rectangle with a 0.5 mm drill. Copper around the hole on the narrow side is (0.65 − 0.5) ÷ 2 = 0.075 mm. JLCPCB publishes 0.18 mm as the minimum for a 2-layer board. The number in the file is below their limit; whether they reject, adjust or build it is theirs to say.

Blocker

U3 (TP4054) supply net VBAT has no capacitor to ground anywhere

Pin 3 VBAT on VBAT.

Why it matters: Chargers, converters and regulators are specified with input and output capacitors. Without them the input can ring when a source is plugged in and the output can oscillate.
Fix: Add the input and output capacitors the datasheet lists (usually 1 to 10 uF ceramic), close to the pins.

Checked by hand: Confirmed. The schematic has no capacitor on VBAT. Pins on that net: the charger, the battery connector, a MOSFET, a resistor and the Pro Micro footprint’s RAW pin. The BOM has no capacitors either: this design has none at all.

Blocker

U3 (TP4054) supply net VBUS has no capacitor to ground anywhere

Pin 4 VDD on VBUS.

Why it matters: Chargers, converters and regulators are specified with input and output capacitors. Without them the input can ring when a source is plugged in and the output can oscillate.
Fix: Add the input and output capacitors the datasheet lists (usually 1 to 10 uF ceramic), close to the pins.

Checked by hand: Confirmed. Same finding on the charger’s input side. VBUS joins the USB connector, a diode, a MOSFET gate, a resistor, the LED, a header and the module’s VBUS pin, with no capacitor to ground.

Blocker

U2 (AP2112K-3.3) has no capacitor on its output net nRF_VDD

No capacitor from nRF_VDD to ground was found anywhere on that net.

Why it matters: Most LDOs use the output capacitor as part of their loop compensation; without it the output can oscillate or ring and the load sees noise instead of a rail.
Fix: Add at least the output capacitor the AP2112K-3.3 datasheet specifies, close to the regulator output pin.

Checked by hand: Confirmed. nRF_VDD carries only the nRF52840 module (VDD and VDDH), a MOSFET and a header pin.

Read these 3

Warning

U2 (AP2112K-3.3) has no capacitor on its input net Net-(D1-K)

No capacitor from Net-(D1-K) to ground was found on that net.

Why it matters: Long supply leads plus the regulator's fast load response can make the input ring or the regulator oscillate.
Fix: Place the datasheet-recommended input capacitor (typically 1 to 10 uF) next to the input pin.

Checked by hand: Confirmed. The input net joins the diode cathode and a MOSFET source only. Shown as a warning, not a blocker, because the input capacitor matters less than the output one when the source is close.

Warning

Input "PROG" on U1 pin 15 (P0.05/AIN3) has a label but nothing drives it

The label exists on this pin only; no other pin or label uses the same name.

Why it matters: An input with no driver floats; it is usually a misspelled label on the sending side.
Fix: Find the other end of "PROG" and make the spelling identical (labels are case-sensitive).

Checked by hand: Confirmed. The label PROG appears once in the whole schematic, on the module’s pin 15. The charger’s own PROG pin sits on an unnamed net. Probably a leftover. KiCad’s ERC also reports a lone label; this one is here because it is the kind of thing that hides a missed connection.

Warning

X1 (32768kHz) has no load capacitors to ground on either pin

Neither crystal terminal has a capacitor to ground.

Why it matters: A Pierce oscillator needs the crystal load capacitance (CL) provided by two capacitors; without them the frequency is off or it fails to start. Exception: MCUs that offer internal load capacitors.
Fix: Add two capacitors of C = 2 x (CL - Cstray) to ground; for CL = 12 pF and ~3 pF stray that is about 18 pF.

Checked by hand: Confirmed, needs a judgment call. No capacitor to ground on either crystal pin. Whether that is a bug depends on the crystal’s load capacitance, and the schematic gives X1 no footprint and no part number, so the check cannot say. Real finding, but one a person should settle against the crystal actually used.

Good to know 4

Note

This board cannot use JLCPCB Economic PCBA; it needs Standard PCBA

parts on both sides (22 top, 2 bottom): Economic PCBA places one side only. Standard PCBA lists a 70 x 70 mm minimum single board (18 x 33 mm here), so a panel is needed.

Why it matters: Standard PCBA has a longer build time (4 days or more against 1 to 3) and different pricing, so the instant quote and lead time you planned around can change.
Fix: Move parts to one side or use larger packages if you want Economic; otherwise budget for Standard.

Note

157 silkscreen text items below JLCPCB legibility minimums (1 mm tall, 0.15 mm stroke)

78 too short (smallest 0.7 mm), 79 too thin (thinnest 0.08 mm).

Why it matters: Smaller text prints as an unreadable blot, so reference designators are useless during assembly or debug.
Fix: Set silkscreen text to 1 mm height and 0.15 mm stroke or larger.

Note

The BOM has no LCSC part number column

Columns found: Designator, Comment, Footprint, Quantity.

Why it matters: JLCPCB assembles by LCSC part number; without it every line has to be matched by hand in the order page, which is slow and error-prone. (Ignore this if you are not ordering assembly from JLCPCB.)
Fix: Add a "LCSC Part #" column (the JLCPCB KiCad plugin or a spreadsheet can fill it).

Note

J1: no ESD/TVS device found on the USB data lines

No TVS diode or ESD array sits on D+/D- (checked the connector side and one series resistor away).

Why it matters: USB ports are touched by people and cables; an ESD hit on bare D+/D- pads commonly kills the MCU USB PHY.
Fix: Add a low-capacitance USB ESD array (for example a USBLC6-2 class part) next to the connector.

Power tree

Regulator	In	Out	Type	Heat limit
`U2` AP2112K-3.3	Net-(D1-K)	nRF_VDD 3.3 V	linear	no datasheet on file

JLCPCB assembly class

This board needs Standard PCBA, not Economic.

parts on both sides (22 top, 2 bottom): Economic PCBA places one side only

22 parts on top, 2 on bottom, 2 copper layers, board 18.1 x 33.3 mm. Limits as published by JLCPCB, read 2026-10-15.

Still needs a person

Software cannot settle these. They are what a human reviewer works through on your board:

Pin functions of every IC against its datasheet 2
Software compared 1 of 4 ICs to datasheet facts it holds (2026-10-15). The rest need someone with the datasheet open:
U1 U3
Pin-1 and polarity rotation at the assembler 14
JLCPCB places each part with its own library rotation, which often differs from the KiCad footprint. Wrong-rotation ICs, LEDs, diodes and polarised capacitors are the most common assembly failure and cannot be seen from the KiCad files.
D1 D2 D3 J1 J2 J3 J4 Q1 Q2 U1 U2 U3 U4 X1
Footprints that did not come with KiCad 6
Downloaded or hand-drawn footprints (EasyEDA imports, vendor libraries) are checked against the symbol pin count only, not against the datasheet land pattern.
U4 U1 J1 J2 JP1 J4
Stock, lifecycle and extended-part fees 20
0 of 20 BOM lines carry an LCSC number. Whether those parts are in stock, active, and Basic or Extended is live JLCPCB data that this offline check cannot see.
Layout that only a person can judge
Return paths, decoupling-loop area, antenna keep-outs, thermal copper, creepage, copper-to-copper clearance (the gap between tracks, pads and pours) and high-speed routing are not judged by this software. Run KiCad's DRC with JLCPCB's minimum clearance for the gap.

What the $49 Fab-order check adds to this board

The report above is everything software could see. For this board a person would also do the following, in two business days:

Parts library: the BOM has no LCSC numbers at all. Match each of the 20 lines to a stocked JLCPCB part, with Basic or Extended noted.
Rotation: check 14 polarised parts (the diode, LEDs, ICs and the USB connector) against JLCPCB’s placement orientation.
Footprints: 6 footprints did not come with KiCad (the E73 module, the USB-C connector and others). Compare each with its datasheet land pattern.
The seven findings: confirmed or dismissed, as above, on your board instead of this one.

Request a Fab-order check, $49 All options