Before You Fab

STM32 BOOT0, NRST, VCAP and VDDA: the pins that decide if it boots

Most first-spin STM32 boards that "do nothing" have a problem on one of five pins. ST documents all of them in its hardware getting-started application notes; this is the condensed version.

BOOT0: pick flash, not the ROM bootloader

At reset, BOOT0 selects where the MCU starts: with BOOT0 low it runs your firmware from main flash; with BOOT0 high it starts the ST system bootloader in system memory (on STM32F1 the BOOT1 pin then chooses between system memory and SRAM). ST's reference circuits connect BOOT0 to ground through a 10 kΩ resistor.

  • Floating BOOT0 picks a boot source at random on each reset - the board works sometimes.
  • BOOT0 tied to 3.3 V always starts the bootloader, never your code.
  • BOOT0 hard-wired to GND boots fine but removes the option of entering the UART/USB bootloader with a jumper or button. That is acceptable if you always program over SWD.

A resistor rather than a direct short lets you add a button or jumper to 3.3 V later. On some newer families (for example STM32G0) BOOT0 shares a pin with a GPIO or SWCLK, and option bytes decide whether the pin is used at all - check the reference manual for your part.

NRST: one capacitor, never a hard connection to VDD

NRST has an internal pull-up. ST's application notes recommend only a 100 nF capacitor to ground to protect against parasitic resets, noting that it can be reduced to 10 nF to limit power consumption. Add a push-button to ground if you want a reset button.

NRST is bidirectional: the MCU itself pulls it low on watchdog, brown-out and software resets, and so do debug probes. Tying NRST straight to VDD fights that internal driver. A very large capacitor stretches the reset pulse and can interfere with the internal reset circuitry, so stay near 100 nF.

VDDA: the analog supply is not optional

VDDA must be connected even if you never use the ADC: depending on the family it also powers analog blocks such as the reset circuit, the RC oscillators and the PLL. ST asks for 100 nF ceramic + 1 µF on VDDA, and VSSA must go to ground. A ferrite bead or small resistor between 3.3 V and VDDA is common to keep digital noise out of the ADC.

VCAP: the core regulator output (STM32F4, F7, H7 and others)

Higher-performance STM32 families generate their 1.2 V core supply with an internal regulator whose output is brought out on VCAP pins. For STM32F4, AN4488 specifies 2.2 µF low-ESR (below 2 Ω) ceramic on each of VCAP_1 and VCAP_2, or a single 4.7 µF (ESR below 1 Ω) when the package only has VCAP_1. Other families have their own values; check the matching getting-started note.

  • No capacitor: the core regulator is unstable; the chip crashes or never starts.
  • VCAP connected to 3.3 V: a common mistake when a symbol pin "looks like a supply". It over-voltages the core. VCAP only ever connects to its capacitor.
  • Two VCAP pins sharing one capacitor: give each pin its own capacitor next to the pin.

VBAT: tie it to VDD if you have no battery

VBAT powers the backup domain (RTC, backup registers, LSE oscillator). Without a coin cell, ST recommends connecting VBAT to VDD with a 100 nF ceramic capacitor. Leaving it floating is the kind of problem that shows up months later as an RTC that misbehaves.

Power pins and decoupling

AN2586 and AN4488 ask for one 100 nF ceramic per VDD pin plus one 4.7 µF minimum (typically 10 µF) for the package. Every VDD and VSS pin must be connected, including the ones hidden on the other side of the symbol. See the decoupling guide.

HSE crystal

If you use an external crystal on OSC_IN/OSC_OUT, each side needs a load capacitor to ground; AN2586 notes values typically in the 5 to 25 pF range, chosen from the crystal's load capacitance. The crystal guide has the formula and a calculator.

USB on STM32F103: the 1.5 kΩ D+ pull-up

A full-speed USB device announces itself with a 1.5 kΩ pull-up on D+. Many STM32 families embed it, but ST's AN4879 lists STM32F102 and STM32F103 among the parts that need it added externally. Some popular low-cost F103 boards use 10 kΩ here, which enumerates on some hosts and not others. Fit 1.5 kΩ from D+ (PA12) to 3.3 V - never to 5 V - or switch it with a transistor if firmware needs to re-enumerate. ST also notes that the full-speed pads do not need external series resistors.

SWD access

Bring SWDIO (PA13), SWCLK (PA14), NRST, 3.3 V and GND to a header, a Tag-Connect footprint or labelled test points. Using PA13/PA14 as general GPIO without a way back in is how a board gets bricked by its first firmware.

Checklist

  1. BOOT0 to GND through 10 kΩ.
  2. NRST: 100 nF to GND, reset button optional, never tied to VDD.
  3. VDDA: 100 nF + 1 µF, VSSA to ground.
  4. VCAP: the specified low-ESR capacitor per pin, nothing else on the net.
  5. VBAT to VDD with 100 nF if there is no battery.
  6. 100 nF per VDD pin plus 4.7-10 µF bulk.
  7. HSE load capacitors from the crystal's CL.
  8. F102/F103 USB: 1.5 kΩ D+ pull-up to 3.3 V.
  9. SWD reachable.

The checker implements each item: BOOT0, NRST, VDDA, VCAP, VBAT, SWD and F1 USB pull-up. Try the STM32F103 sample on the home page to see them run.

Primary sources